The present invention relates to semiconductor devices having accurately dimensioned interconnection patterns. The present invention is particularly applicable to ultra large-scale integrated (ULSI) circuit devices having features in the deep sub-micron regime.
As integrated circuit geometries continue to plunge into the deep sub-micron regime the requirements for dimensional accuracy become increasingly difficult to satisfy. Integration technology is considered one of the most demanding aspects of fabricating ULSI devices. Demands for ULSI semiconductor wiring require increasingly denser arrays with minimal spacings between narrower conductive lines. Implementation becomes problematic in manufacturing semiconductor devices having a design rule of about 0.12 micron and under.
Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed interlayer dielectrics and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, conductive patterns on different levels, i.e., upper and lower levels, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor xe2x80x9cchipsxe2x80x9d comprising five or more levels of metallization are becoming more prevalent as feature sizes shrink into the deep sub-micron regime.
A conductive plug filling a via hole is typically formed by depositing an interlayer dielectric (ILD) on a conductive level comprising at least one conductive feature, forming an opening through the ILD by conventional photolithographic and etching techniques, and filling the opening with a conductive material. Excess conductive material or the overburden on the surface of the ILD is typically removed by chemical-mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the ILD and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact hole or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a dual, to simultaneously form a conductive plug in electrical contact with an upper conductive line.
Copper (Cu) and Cu alloys have received considerable attention as alternative metallurgy to aluminum (A1) in interconnect metallizations. Cu is relatively inexpensive, easy to process, and has a lower resistively than A1. In addition, Cu has improved electrical properties vis-à-vis tungsten (W), making Cu a desirable metal for use as a conductive plug as well as conductive wiring. However, due to Cu diffusion through dielectric materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier materials include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium-tungsten (TiW), Tungsten (W), tungsten nitride (WN), Tixe2x80x94TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the ILD, but includes interfaces with other metals as well.
The dielectric constant of materials currently employed in the manufacture of semiconductor devices for an interlayer dielectric (ILD) ranges from about 3.9 for dense silicon dioxide to over 8 for deposited silicon nitride. The value of a dielectric constant expressed herein is based upon a value of one for a vacuum. In an effort to reduce interconnect capacitance, dielectric materials with lower values of permitivity have been explored. The expression xe2x80x9clow-kxe2x80x9d material has evolved to characterize materials with a dielectric constant less than about 3.9, e.g., about 3.5 or less. One type of low-k material that has been explored are a group of flowable oxides which are basically ceramic polymers, such as hydrogen silsesquioxane (HSQ). HSQ-type flowable oxides have been considered for gap filling between metal lines because of their flowability and ability to fill small openings.
There are several organic low-k materials, typically having a dielectric constant of about 2.0 to about 3.8, which offer promise for use as an ILD. Organic low-k materials which offer promise are carbon-containing dielectric materials such as FLARE 2.0(trademark) dielectric, a poly(arylene)ether available from Allied Signal, Advanced Microelectronic Materials, Santa Clara, Calif., BCB (divinylsiloxane bis-benzocyclobutene) and Silk(trademark) an organic polymer similar to BCB, both available from Dow Chemical Co., Midland, Mich.
Cu interconnect technology, by and large, has been implemented employing damascene techniques, wherein an ILD, such as a silicon oxide layer, e.g., derived from tetraethyl orthosilicate (TEOS) or silane, or a low-k material, is formed over an underlying metal level containing metal features, e.g., Cu or Cu alloy features with a silicon nitride capping layer. A damascene opening, e.g., via hole, trench, or dual damascene opening, is then formed in the ILD. A barrier layer and optional seedlayer are then deposited, followed by Cu deposition, as by electrodeposition or electroless deposition.
In implementing conventional dual damascene techniques wherein the trench is formed before forming the via (trench first-via last), a via mask, which also serves as an etch stop, is formed on a first dielectric layer overlying capped metal feature. The via mask typically formed of silicon oxide, silicon nitride or silicon oxynitride, and is chosen for its high etch selectivity with respect to the overlying second dielectric layer which is then deposited on the via mask/etch stop layer. A photoresist mask is then formed over the second dielectric layer, and anisotropic etching is conducted to form a trench through the second dielectric layer stopping on the via mask/etch stop layer and to form a via hole through first dielectric layer. However, the via mask/etch stop layer exhibits relatively poor anti-reflective properties, thereby reducing the dimensional accuracy of the resulting interconnection.
As miniaturization proceeds apace with an attendant shrinkage in the size of metal lines, e.g., metal lines having a width of about 0.3 micron and under, e.g., about 0.2 micron and under, it becomes increasingly difficult to achieve the requisite dimensional accuracy of the metal lines, particularly when implementing dual damascene techniques. Accordingly, there exists a need for interconnection methodology enabling the formation of metal features, such as metal lines, with high dimensional accuracy. There exists a particular need for dual damascene methodology enabling the formation of accurately dimensional metal lines having a width of about 0.3 micron and under, e.g., about 0.2 micron and under.
An advantage of the present invention is a semiconductor device comprising an interconnection pattern with high dimensional accuracy.
Another advantage of the present invention is a method of manufacturing a semiconductor device comprising an interconnection pattern with accurately dimensioned metal lines.
Additional advantages and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned by practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a first dielectric layer on a capping layer overlying a lower metal feature of a lower metal level; forming a silicon carbide via mask/anti-reflective coating (ARC) on the first dielectric layer; forming a second dielectric layer on the silicon carbide via mask/ARC; and etching to form: a trench through the second dielectric layer stopping on the silicon carbide via mask/ARC; and a via hole through the silicon carbide etch stop layer/ARC and through the first dielectric layer exposing a portion of the capping layer.
Embodiments of the present invention include chemical vapor depositing a layer of silicon carbide, having an extinction coefficient (k) of about xe2x88x920.2 to about xe2x88x920.5, on the first dielectric layer, forming a photoresist mask on the silicon carbide layer, etching an opening in the silicon carbide layer to form the silicon carbide via mask/ARC, forming a photoresist mask on the second dielectric layer and etching to form a dual damascene opening comprising the trench communicating with the underlying via hole. Embodiments of the present invention also include the use of a silicon carbide capping layer/ARC on the underlying metal feature and the use of low-k dielectric layers. After depositing a suitable barrier metal layer and seedlayer, Cu or a Cu alloy is deposited, as by electrodeposition or electroless deposition. CMP is then conducted followed by deposition of a suitable capping layer, such as silicon nitride. As employed throughout this disclosure, the symbol Cu is intended to encompass high purity elemental copper as well as Cu-based alloys, such as Cu alloys containing minor amounts of tin, zinc, manganese, titanium, germanium, zirconium, strontium, palladium, magnesium, chromium and tantalum.
Additional advantages of the present invention will become readily apparent to those having ordinary skill in the art from the following detailed description, wherein embodiments of the present invention are described simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and descriptions are to be regarded as illustrative in nature and not as restrictive.